Field of the Invention
The invention relates to an integrated memory having a cell array with a plurality of memory cells located at intersecting points of associated word and bit lines. A row decoder is provided for addressing the word lines in response to received row address signals. The row decoder has amplifiers for outputting decoder signals onto the word lines.
Such an integrated memory is described in Published, European Patent Application EP 0 428 785 A1, for example, where driver stages for driving the word lines are situated between cell array blocks. The driver stages drive output signals from word decoders.
In the so-called "folded bit line structure" of the prior art, two bit lines of a bit line pair run parallel to one another in a wiring plane of the memory. During memory accesses, the two associated bit lines carry opposite potentials in each case, namely logic 1 and logic 0. The interfering influences caused by the bit lines on the word lines which cross them are at least partly canceled out on account of their opposite potentials. A so-called "vertical folded bit line structure" is conceived of, inter alia, for future memories. In this structure, the two bit lines of a bit line pair do not run in a common wiring plane of the memory but rather above one another in different wiring planes. Therefore, compensation of the interfering influences--caused because of capacitive coupling--on the word lines which cross the bit lines no longer occurs in such memories. In memories of this type, therefore, the signals present on the word lines could be subjected to interference in an impermissible manner.